Meaning
Verification metrics quantify the percentage of components and electrical nets on a printed circuit board that are accessible for automated testing. High levels of in circuit testing coverage ensure that manufacturing defects such as shorts, opens, missing components or incorrect polarities are detected before the product reaches the customer. This measurement is calculated by comparing the number of testable nodes to the total number of nodes in the design.
Physical access for test probes remains the primary constraint on this metric.
Access Constraint
Dense layouts with fine pitch components often lack the space required for dedicated test pads. Designers improve in circuit testing coverage by adding via-in-pads or specific probe points to the copper layers. If a net cannot be touched by a physical probe, the tester cannot verify the presence or value of the components connected to it.
Boundary scan technology sometimes supplements physical probing to reach internal nodes within complex integrated circuits.
Fault Detection
Manufacturing errors often involve incorrect resistor values or misaligned capacitors that are difficult to find with functional testing alone. A high in circuit testing coverage score indicates that the majority of these passive components can be individually measured and verified against the bill of materials. This process catches assembly issues early, which reduces the cost of repair and prevents secondary damage to the board.
Yield reports track the types of faults found to identify trends in the assembly line and to justify improvements in the soldering process or component handling.
Design Optimization
Trade-offs between board size and testability occur throughout the development process. Engineers aim for maximum in circuit testing coverage while maintaining a compact form factor for the end product. Using smaller probe diameters or double sided testing fixtures can increase the accessible area of the board.
The final test plan balances the time required for testing against the risk of undiscovered defects.